Designers and fabricators of integrated circuits (ICs) strive to increase speeds of operation of circuits in ICs. A common method of increasing operating speed is to increase current supplied by MOS transistors, known as drive current. One technique for increasing drive current is to increase electron mobilities in inversion layers of n-channel MOS transistors and increase hole mobilities in inversion layers of p-channel MOS transistors by increasing stress on the silicon lattice in the inversion layers. This is frequently accomplished by forming a dielectric layer on the MOS transistors, typically containing silicon nitride, known as the pre-metal dielectric (PMD) liner, with compressive stress. The increase in drive currents achievable by this method is limited by the thickness of the PMD liner, which is constrained by minimum gate spacing and other considerations.